CVE-2020-0574
CVE.org · Published
- Record status
- Published
- Identifier year (not publication year)
- 2020
- Source publication
- Source updated
- Imported by cveboard
- Source snapshot
- cve_2026-10-24_midnight_baseline ·
CNA source text (English)
Improper configuration in block design for Intel(R) MAX(R) 10 FPGA all versions may allow an authenticated user to potentially enable escalation of privilege and information disclosure via physical access.
Scoped product and version facts
Fix information unknown; no fixed version is derived here. Missing information does not prove that no fix exists.
Exploitation unknown; this catalogue does not assess exploitation.
Intel(R) MAX(R) 10 FPGA
- Vendor
- Intel
- Product
- Intel(R) MAX(R) 10 FPGA
- Platforms
- Unknown
- Default status
Unknown
| Version (version) | Status (status) | Version scheme (versionType) | Exclusive end (lessThan) | Inclusive end (lessThanOrEqual) | Status changes (at → status) |
|---|---|---|---|---|---|
| All versions | affected | Unavailable | Unavailable | Unavailable | None listed |
| See advisory https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00349.html | affected | Unavailable | Unavailable | Unavailable | None listed |